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AQ: Switching frequency selection

Switching frequency selection is actually a tradeoff, and follows the below guidelines:

  1. Lower frequency (Eg 30kHz) means bulkier magnetics and capacitors; Higher frequency (Eg 1Mhz)) means smaller parts, hence more compact PSU.
  2. Stay away from exact 150kHz as this is the low end of any EMI compliance; So, if your frequency happens to be exactly 150kHz, then your PSU will be a strong emitter; For many commercial low cost PSUs, 100 KHz has been used for many years, which is why many inductors and capacitors are specified at 100kHz.
  3. Higher frequency >/= 1MHz converters provide for better transient response. Obviously, the control IC should be capable of supporting. There are plenty of resonant converters available.
  4. Higher frequency results in higher switching losses; To control that, you will need faster switching FETs, Diodes, capacitors, magnetics and control ICs.
  5. Higher frequency MAY result in more broadband noise; its not always true, since noise can be controlled by good PCB layout and good magnetics designs.

Board power DC/DC converters are commonly built using 1MHz switchers.
Chassis power Telecom/Server PSUs seem to stay with 100-300KHz range.

Manufacturers are able to achieve exceptional density by virtue of High frequency resonant topologies, but they have to achieve high efficiencies too; Else, they will generate so much heat that they cannot meet UL/IEC safety requirements.
In some cases, they will leave the thermal problem to the user.  Usually, the first few paragraphs of any reference design discusses the tradeoffs.

AQ: How to get confidence while powering ON an SMPS prototype?

I never just put power to a first prototype and see what happens. Smoke and loud sounds are the most likely result and then you just know that something was not perfect. So how would you test the next prototype sample?

A good idea is to put supply voltage to your control circuit from an external supply first – often something like 12V. Check oscillator waveform, frequency, gate pulses etc. If possible, use another external power supply to put a voltage to your output. Increasing this voltage slowly, you should see the gate pulses go from max. to min. duty cycle when passing the desired output voltage. If this does not happen, check your feedback path, still without turning main power on.

If everything looks as expected, remove the external supply from the output but keep the control circuit powered from an external source. Then SLOWLY turn up the main input voltage while using your oscilloscope to monitor the voltage waveforms in the power circuit and a DC voltmeter to monitor output voltage etc. Keep an eye on the ampere-meter on the main power source. If something suspicious occurs, stop increasing input further and investigate what’s happening while the circuit is still alive.

With a low load you should normally expect the output voltage to hit the desired value soon, at least in a flyback converter. Check that this happens. Then check what happens with a variable load – preferably electronic.

If you did not calculate your feedback loop, very likely you will see self oscillation (normally not destructive). If you don’t, use the step load function in your electronic load to check stability. If you see a clear ringing after a load step, you still have some work to do in your loop. But feedback and stability is another huge area which Mr. Ridley has taught us a lot about.

And yes – the world needs powerful POWER ENGINEERS desperately!

AQ: Hysteretic controller

We can see that the hysteretic controller is a special case of other control techniques. For example, “sliding mode control” usually uses two state variables to determine one switching variable (switch ON or OFF). So the hysteretic controller is a special case of “1-dimensional” sliding mode. In general, there are many techniques under the name of “geometric control” that can be used to prove the stability of a general N-state system under a given switching rule. So I believe that you can apply some of these techniques to prove the stability of the hysteretic controller, although I have not tried to do this myself. The book “elements of power electronics” by Krein discusses that in chapter 17.

But I can talk more about one technique that I have used and in my opinion is the most general and elegant technique for non-linear systems. It is based on Lyapunov stability theory. You can use this technique to determine a switching rule to a general circuit with an arbitrary number of switches and state variables. It can be applied to the simple case of the hysteretic controller (i.e. 1 state variable, 1 switching variable) to verify if the system is stable and what are the conditions for stability. I have done this and verified that it is possible to prove the stability of hysteretic controllers, imposing very weak constraints (and, of course, no linearization needed). In a nutshell, to prove the system stable, you have to find a Lyapunov function for it.

What can expand is to go beyond a simple window comparator for hysteretic control.

#1) control bands, or switching limits can be variable and also part of a loop, especially if one wants to guarantee a nearly fixed frequency.

#2) using a latch or double latch after the comparator(s), one can define (remember) the state and define operations such as incorporating fixed Ton or Toff periods for additional time control… this permits the “voltage boost” scenario you previously said could not be done. This also prevents common “chaos” operation and noise susceptibility that others experience with simpler circuits.

#3) additional logic can assure multiphase topologies locked to a system clock and compete very well with typical POL buck regulators for high-end processors that require high di/dt response.

Time or state domain control systems such as this, can have great advantages over typical topologies. There really is no faster control method that provides a quicker load response without complete predictive processing, yet that can also be applied to hysteretic control.

AQ: Experience: Power Supply

My first big one: I had just joined a large corporation’s central R and D in Mumbai (my first job) and I was dying to prove to them that they were really very wise (for hiring me). I set up my first AC-DC power supply for the first few weeks. Then one afternoon I powered it up. After a few minutes as I stared intently at it, there was a thunderous explosion…I was almost knocked over backwards in my chair. When I came to my senses I discovered that the can of the large high-voltage bulk cap had just exploded (those days 1000uF/400V caps were real big)…the bare metal can had taken off like a projectile and hit me thump on the chest through my shirt (yet it was very red at that spot even till hours later). A shower of cellulose and some drippy stuff was all over my hair and face. Plus a small crowd of gawking engineers when I came to. Plus a terribly bruised ego in case you didn’t notice. Now this is not just a picturesque story. There is a reason why they now have safety vents in Aluminum Caps (on the underside too), and why they ask you never never to even accidentally apply reverse polarity, especially to a high-voltage Al cap. Keep in mind that an Al Elko is certainly damaged by reverse voltage or overvoltage, but the failure mechanism is simply excessive heat generation in both cases. Philips components, in older datasheets, used to actually specify that their Al Elkos could tolerate an overvoltage of 40% for maybe a second I think, with no long-term damage. And people often wonder why I only use 63V Al Elkos as the bulk cap in PoE applications (for the PD). They suggest 100V, and warn me about surges and so on. But I still think 63V is OK here, besides being cheap, and I tend to shun overdesign. In fact I think even ceramic caps can typically handle at least 40% overvoltage by design and test — and almost forever with no long term effects. Maybe wrong here though. Double check that please.

Another historic explosion I heard about after I had left an old power supply company. I deny any credit for this though. My old tech, I heard, in my absence, was trying to document the stresses in the 800W power supply which I had built and left behind. The front-end was a PFC with four or five paralleled PFC FETs. I had carefully put in ballasting resistors in the source and gates of each Fet separately, also diligently symmetrical PCB traces from lower node of each sense resistor to ground (two sided PCB, no ground plane). This was done to ensure no parasitic resonances and good dynamic current sharing too. There was a method to my madness it turns out. All that the tech did was, when asked to document the current in the PFC Fets, placed a small loop of wire in series with the source of one of these paralleled Fets. That started a spectacular fireworks display which I heard lasted over 30 seconds (what no fuse???), with each part of the power supply going up in flames almost sequentially in domino effect, with a small crowd staring in silence along with the completely startled but unscathed tech (lucky guy). After that he certainly never forgot this key lesson: never attempt to measure FET current by putting a current probe in its source— put it on the drain side. It was that simple. The same unit never exploded after that, just to complete the story.

AQ: Constant on-time control

There are three different more or less widely used types of constant on-time control. The first one is where the off-time is varied with an error signal. A loop with this type of control has a control-to-output voltage frequency response (or Bode plot if you prefer) similar to that of the constant-frequency voltage-mode control. The second one is where the off-time is terminated with a comparator that monitors the inductor current, and when that current goes below a level set by the error signal, the switch is turned on. This control (also called constant on-time valley-current control) has a control-to-output voltage frequency response similar to the constant-frequency valley-current control. The main difference is that its inner current-control loop does not suffer from the subharmonic instability of the constant-frequency version, so it does not require a stabilizing ramp and the control-to-output voltage response does not show the half-frequency peaking. The third version is where the off-time is terminated when the output voltage (or a fraction of it) goes below the reference voltage. This control belongs to the family of ripple-based controls and it cannot be characterized with the usual averaging-based control-to-output frequency response, for the reason that the gain is affected by the output ripple voltage itself.

As for the hysteretic control, the current-mode version is a close relative of the constant on-time valley-current-control. The version that uses the output ripple voltage instead of the inductor current ripple for turning on and off the switch (also called “hysteretic regulator”) is a close relative of the constant on-time ripple-based control.

Although the ripple-based control loops cannot be characterized with the usual Bode plots, the converters can still be unstable, but not in the meaning of the traditional control-loop instability that power-supply engineers are used to. Furthermore the hysteretic regulator is essentially unconditionally stable. The instabilities with ripple-based control are called “fast-scale” because the frequency of the instability is closely related to the switching frequency (either subharmonic, similar to the inner-loop instability of some of the current-mode controller, or chaotic in nature).

The paper I wrote a couple of years ago (“Ripple-Based Control of Switching Regulators—An Overview”) is a good introduction to ripple-based control and discusses some of the stability issues. There are also quite a few papers with detailed analyses on the stability of converters with feedback loops where the ripple content of the feedback signal is significant.

AQ: Power supply prototype failures

I remember my very first power supply. They threw me in the deep end in 1981 building a multi-output 1 kW power supply. I was fresh from college, thought i knew everything, and consumed publications voraciously to learn more. Exciting times.

But nothing prepared me for the hardware trials and tribulations. We built things and they blew up. Literally. We would consume FETs and controllers at an alarming rate. The rep from Unitrode would come and visit and roll his eyes when we told him we needed another dozen controllers since yesterday.

The reasons for failure were all over the map . EMI, heat, layout issues, design issues, bad components (we had some notorious early GE parts – they exited the market shortly afterwards.)
Some of the issues took a few days to fix, some of them took weeks. We had two years to get the product ready, which was faster than the computer guys were doing their part, so it was OK.

90% of the failure issues weren’t talked about in any paper, and to this day, most of them still aren’t.

So, fast forward to today, 32 years later. I still like to build hardware – you can’t teach what you don’t practise regularly, so I keep at it.

With all the benefit of 3 decades of knowledge I STILL blow things up. Everything progresses along fine, then i touch a sensitive circuit node, or miss some critical design point and off it goes. I’m faster now at finding the mistakes but I still find there are new ones to be made. And when it blows up with 400 V applied, it’s a mess and a few hours to rebuild. Or you have to start over sometimes, if the PCB traces are vaporized.

So my first prototype, while on a PC board, always includes the controller in a socket because I know I will need that. Magnetics too, when possible, I know I’ll revise them time and again to tweak performance. PC boards will be a minimum of two passes, probably three.

AQ: FETs in ZVS bridge

Had run into a very serious field failure issue a decade ago due to IXYS FETs used in a phase-shifted ZVS bridge topology. Eventually, the problem was tracked to failure of the FETs’ body diode when the unit operated at higher ambient temperature.

When FETs were first introduced for use in hard switching applications, it was quickly discovered that under high di/dt commutating conditions, the parasitic bipolar transistor that forms the body diode can turn on resulting in catastrophic failure (shorting) of the FET. I had run into this issue in the mid ’80s and if memory serves me correctly, IR was a leader in making their FET body diodes much more robust and capable of hard commutation. Having had this experience with FET commutation failures and after exhausting other lines of investigation which showed no problem with the operation of the ZVS bridge, I built a tester which could establish an adjustable current through the body diode of the FET under test followed by hard commutation of the body diode.

Room temperature testing of the suspect FET showed the body diode recovery characteristic similar to that of what turned out to be a more robust IR FET. Some difference was seen in the diode recovery as the IXYS FET was a bit slower and did show higher recovered charge. However, was unable to induce a failure in either the IXYS or IR FET even when commutating high values of forward diode current up to 20A when testing at room temperature.

The testing was then repeated in a heated condition. This proved to be very informative. The IXYS FETs were found to fail repeatedly with a case temperature around 80C and forward diode current prior to commutation as low as 5A. In contrast, the IR devices were operated to 125C case temp with forward diode currents of 10A without failure.

This confirmed a high temperature operating problem of the IXYS FETs associated with the body diode. Changing to the more robust IR devices solved the field failure issue.
Beware when a FET datasheet does not provide body diode di/dt limits at elevated ambient.

A more complete explanation of the FET body diode failure mechanism in ZVS applications can be found in application note APT9804 published by Advanced Power Technology.

I believe FETs can be reliably used in ZVS applications if the devices are carefully selected and shown to have robust body diode commutation characteristics.

AQ: Heavily discontinuous mode flyback design

With a heavily discontinuous mode flyback design, the transformer’s ac portion of current can be larger than the dc portion. When a high perm material is used for the transformer core, the required gap can be quite large in order to reach the low composite permeability required while the core size will likely be driven by winding and core loss considerations rather than just simply avoiding saturation. Normally the gap is put in the center leg only (with E type topology cores) in order to minimize the generation of stray fields. However, in designs such as yours (high ac with a high perm core) the needed core gap can lead to a relatively large fringing zone through which foil or solid wire may not pass without incurring excessive, unacceptable loss. Possible solutions are to use Litz wire windings or inert spacers (e.g., tape) around the center leg in order to keep the windings far enough away from the gap (the rule of thumb is 3 to 5 gap lengths, which can eat up a lot of the window area).

It is mainly for these reasons that placing half the gap in an E type core’s outer legs might be worth the trouble of dealing with the magnetic potential between the core halves (and you have seen first hand what trouble an ill designed shield band can be).

To avoid eddy current losses, the shield band should be spaced well away from the outer leg gap, probably 5 gap lengths or more. Also to be a really effective magnetic shield, it should be 3 to 5 gap lengths thick.

Bear in mind that with a high frequency, high ac current inductor design proximity effects in the winding may become very significant. This is why many of these type of inductors have single layer windings or winding wound with Litz wire (foil is the worst winding type here). One advantage of an equally gapped E type core design is that the proximity effect on the windings is significantly less because there are two gaps in series (a quasi distributed gapped core design). Not only layer-to-layer, but turn-to-turn proximity effects can sometimes be problematic in an ac inductor (or flyback) design. Just as with the gap, these are reduced by adding appropriate spacing, for example making the winding coil loose or winding it bifilar with a non-conductive filament.

AQ: Power converter trend

The trend toward lower losses in power converters is not apparent in all of the applications of power converters. It is also not apparent that the power converter solution and its losses for a given market will be the same when it comes to losses. In terms of the market shift that you mention, Prof. the answer is probably that each market is becoming split into a lower efficiency and higher efficiency solution.

From my limited view the reason for this is the effort and time required to do the low loss development. The early developers of low loss converters are now ahead and those that were slower may never catch them. This gap is in a number of converter markets widening, with both higher loss and lower loss offerings continuing to be used and sold. This split is not apparent with different levels of development or geographically.

Some markets already have very efficient solutions, other markets not so efficient and others had high power loss solutions. The customers accepted these solutions. The path to lower loss converters is for some markets not yet clear and in some markets the requirement may never actually become real.

It does seem that there is a real case to make for any power converter market splitting in two as the opportunities presented by lowering the power loss are taken.

All low loss converters present significant challenges and are all somewhat esoteric.

For me power supply EMI control consists of designing filtering for differential and common mode conducted emissions. The differential mode filtering attenuates the primary side differential lower frequency switching current fundamental & harmonic frequencies. The common mode filtering provides a low impedance return path for high frequency noise currents resulting from high dV/dt transitions during switching transitions present on the power semiconductors (switching mosfet drain, rectifier cathods). These noise currents ring at high frequencies as they oscillate in the uncontrolled parasitic inductance and capacitance associated with their return to source path. Shortening and damping this return path allows the high frequency noise currents to return locally instead of via the measurement copper bench and conducted emi current or voltage (LISN) probe as well as providing a more damped ringing frequency. Shorting this return path has the added benefit of decreasing radiated emissions. In addition proper layout of the power train so as to minimize the loop area associated with both the primary and secondary side switching currents minimizes the associated radiated emissions.

When I mentioned the criticism of resonant mode converter as related to the challenges of emi filitering I was referring to the additional differential mode filtering required. For example if you take a square wave primary side current waveform and analyze the differential frequency content the fundamental magnitude with be lower and there will be higher frequency components as compared to a purely resonant approach at the same power level. It is normally the lower frequency content that has to be filtered differentially.

Given these differences the additional emi filtering volume/cost of the resonant approach may pose a disadvantage.

AQ: flyback & boost applications

For flyback & boost applications, powder cores such as Kool-mu, Xmu, etc… are usually best performing and lowest cost. Even these may need to be gapped and if CCM operation is required, a “stepped-gap” is preferred to allow a large load compliance. Center stepped gaps reduce the fringe flux greatly as there is never a complete gap, only localized saturation. This permits the inductor’s value to “swing” more and accommodate the required operation.
With only the center leg with a gap, the outer copper band can be applied without significant loss.

To explore further, dissimilar core materials can be used in parallel, ferrite & powdered types, such that different materials provide function at different operating points within the same construction. Some decades ago, we had some high power projects that utilized fixed magnets within a ferrite’s gap to provide a flux bias offset for a forward topology.

Abe Pressman wasn’t big on exploring magnetic losses, however he operated at lower frequencies than are typical today. MPPs are great with large DC bias, but suffer high loss if AC swing is large and fast. Toroids also have the least efficient winding window, however, they are best to mitigate emi.